This processor is pretty wonky. These are just the instructions, for now. Sooner or later I might get enough information up to serve as a development manual. Probably not, but a man can hope, right? :)
Instruction word format
| ECC | Parity | A | B | C | D | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| – | – | – | – | – | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
Instruction set
| No. | Mnemonic | Type | A, B | C | D | Description |
|---|---|---|---|---|---|---|
| Decision Orders | ||||||
| 1 | RY- | 1 | * | 0 | - | Read and regenerate BGS at Y specified by D (X given by BGX). |
| 2 | RX- | 1 | * | 1 | - | Read and regenerate BGS at X specified by D (Y given by BGX). |
| 3 | EY- | 1 | * | 2 | - | Read and erase BGS at Y specified by D (X given by BGX). |
| 4 | EX- | 1 | * | 3 | - | Read and erase BGS at X specified by D (Y given by BGY). |
| 5 | CY- | 1 | * | 4 | - | Read and change BGS at Y specified by D (X given by BGX). Suffix refers to reading before change. |
| 6 | CX- | 1 | * | 5 | - | Read and change BGS at X specified by D (Y given by BGY). Suffix refers to reading before change. |
| 7 | RP- | 1+ | * | 6 | - | Read and regenerate the BGS at address stored in BG. |
| 8 | RYB- | 1 | * | 7 | - | Read and regenerate at Y specified by D (X given by BGX). Store Y in BGY. |
| 9 | RXB- | 1 | * | 8 | - | Read and regenerate at X specified by D (Y given by BGY). Store X in BGX. |
| 10 | EYB- | 1 | * | 9 | - | Read and erase at Y specified by D (X given by BGX). Store Y in BGY. |
| 11 | EXB- | 1 | * | 10 | - | Read and erase at X specified by D (Y given by BGY). Store X in BGX. |
| 12 | RFF- | 2 | * | 11 | - | Read miscellaneous flip-flop specified by D. |
| 13 | RS- | 3 | * | 12 | - | Read the scanner at address preset in S. |
| 14 | MY- | 4+ | * | 13 | - | Match the Y bits of M with the Y bits of the FFG specified by D. Match = 1; mismatch = 0. |
| 15 | MX- | 4+ | * | 14 | - | Match the Y bits of M with the X bits of the FFG specified by D. Match = 1; mismatch = 0. |
| 16 | MB- | 4 | * | 15 | - | Match the contents of M with the contents of the FFG specified by D. Match = 1; mismatch = 0. |
| Decision Order Modifier Suffixes | ||||||
| - | -0 | - | 0, 0 | - | - | If 0 is read, take next order from address given by T1. |
| - | -1 | - | 1, 0 | - | - | If 1 is read, take next order from address given by T1. |
| - | -02 | - | 0, 2 | - | - | If 0 is read, take next order from address given by T2. |
| - | -12 | - | 1, 2 | - | - | If 1 is read, take next order from address given by T2. |
| - | -0A | - | 0, 1 | - | - | Add 1 to Y part of contents of T1. Then, if 0 is read, take next order from address given by T1. |
| - | -1A | - | 1, 1 | - | - | Add 1 to Y part of contents of T1. Then, if 1 is read, take next order from address given by T1. |
| Nondecision Orders | ||||||
| 17 | W0Y | 5 | 7, 3 | 0 | - | Write a 0 on the BGS at the Y address specified by D (X given by BGX). |
| 18 | W1Y | 5 | 7, 3 | 1 | - | Write a 1 on the BGS at the Y address specified by D (X given by BGX). |
| 19 | W0X | 5 | 7, 3 | 2 | - | Write a 0 on the BGS at the X address specified by D (Y given by BGY). |
| 20 | W1X | 5 | 7, 3 | 3 | - | Write a 1 on the BGS at the X address specified by D (Y given by BGY). |
| 21 | W0P | 5+ | 7, 3 | 4 | - | Write a 0 on the BGS at the address contained in BG. |
| 22 | W1P | 5+ | 7, 3 | 5 | - | Write a 1 on the BGS at the address contained in BG. |
| 23 | W0FF | 6 | 7, 3 | 6 | - | Write a 0 in the miscellaneous flip-flop specified by D. |
| 24 | W1FF | 6 | 7, 3 | 7 | - | Write a 1 in the miscellaneous flip-flop specified by D. |
| 25 | RYFA | 7 | 3, 0 | - | - | Read and regenerate the BGS at the Y address specified by D, and transport the bit to the access flip-flop specified by C (X given by BGX). |
| 26 | WFAY | 8 | 3, 1 | - | - | Transport the contents of the access flip-flop specified by C to the BGS at the Y address specified by D (X given by BGX). |
| 27 | ST1 | 9 | 4, - | - | - | Set up transfer register 1 to the number specified by B, C, D. |
| 28 | SA1 | 9 | 5, - | - | - | Set up access register 1 to the number specified by B, C, D |
| 29 | SA2 | 9 | 6, - | - | - | Set up access register 2 to the number specified by B, C, D |
| 30 | SY | 9+ | 7, 3 | 10 | - | Set up BGY to the number specified by D. |
| 31 | SX | 9+ | 7, 3 | 11 | - | Set up BGX to the number specified by D. |
| 32 | G | 10 | 3, 3 | - | - | Gate the contents of the FFG specified by C to the FFG specified by D. |
| 33 | T | 11a | 2, - | - | - | Transfer to the address specified by B, C, D. |
| 34 | TFG | 11b | 7, 3 | 12 | - | Transfer to the address contained in the FFB specified by D. |
| 35 | AY | 12 | 7, 3 | 13 | - | Add 1 to BGY. |
| 36 | AX | 12 | 7, 3 | 14 | - | Add 1 to BGX. |
| 37 | RGY | 13 | 7, 3 | 15 | - | Regenerate the BGS at the Y address specified by D (X given by BGX). |
| 38 | RGX | 13 | 7, 3 | 16 | - | Regenerate the BGS at the X address specified by D (Y given by BGY). |
* Modifier code
+ Size of address not same as specified in Table VI.