“Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in Three-Dimensional Integrated Circuits,”, with Zhou, Lili et al, Computer Design, 2007. (ICCD '07) International Conference on , pp.194-201.

“Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in Three-Dimensional Integrated Circuits”, Invited Paper, International Conference on Computer Design, Lake Tahoe, CA, October 2007

“Maximizing the Throughput-Area Efficiency of Fully-Parallel Low-Density Parity-Check Decoding with CSlow Retiming and Asynchronous Deep Pipelining”, International Conference on Computer Design, Lake Tahoe, CA, October 2007