I am currently involved in the Mosiac project under Professor Scott Hauck. Its goal is to explore the CGRA architecture space to determine the ideal design for a wide array of benchmark applications. These CGRAs can range from a FPGA routed at the word level all the way up to a sea of high end CPUs, DSP cores,  and/or specialized ASIC functions. They are not necessarily homogeneous. Along the way we are building infrastructure to program the CGRAs in a hardware-agnostic manner. I have been working with Aaron Wood and Brian Van Essen to characterize the building blocks and determine the performance and energy use of several of these architectures.

Previously, I worked under Professor Richard Shi on CASCADE, which had the goal of making a high speed LDPC decoder on a fabrication process involving multiple device layers. I worked on DFT, testing, and final integration.